Formerly Janakpur Engineering College (JEC)Affiliated to Tribhuvan University
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IOE syllabus 2080

ENEX 152 Digital Logic

BCT Semester 2 and BEI Semester 2 · Tribhuvan University, Institute of Engineering

Digital Logic (ENEX 152) is the Semester 2 course for Computer and BEI students on how digital circuits are built, from logic gates and Boolean algebra to flip-flops, counters, state machines and the TTL and CMOS chips that implement them.

  • 3 credits
  • 45 lecture hours
  • 8 chapters
  • 150 marks

About the subject

What Digital Logic is for

Every computer, phone and controller is built from the circuits taught here. The course starts with number systems and codes, then builds up: gates combine into adders, multiplexers and decoders; flip-flops add memory; registers and counters organise that memory; and state machines give a circuit behaviour over time.

It is a design course as much as a theory course. By the end, a student can take a word description, such as detecting a two-bit sequence on an input line, and turn it into a state diagram, a table, simplified equations and a working circuit.

This course mainly focuses on study, analyze basic principle, design and applications of digital circuitries in various fields. It also shows an important branch of the electronics that revolutionizes the modern digital world.

IOE's course objective for ENEX 152
Taught to
BCT, Semester 2 (Year I, Part II) and BEI, Semester 2 (Year I, Part II)
Weekly
3 lecture, 1 tutorial, 3 practical hours
Marks
Theory 40 internal + 60 final (3-hour exam); practical 50 internal; 150 in total

Full syllabus

The complete ENEX 152 outline, with how to study each chapter

All 8 chapters and 68 topics as IOE lists them, each with ICE's advice on approaching it.

1Introduction5 hours

Number systems, codes, and 1's and 2's complement. Conversions must become automatic, because every later chapter uses them.

  • 1.1 Digital versus analog signals
  • 1.2 Logic level diagram
  • 1.3 Digital integrated circuits (ICs)
  • 1.4 Clock triggering systems
  • 1.5 Digital system applications
  • 1.6 Digital codes and conversions
    • Decimal, binary, octal and hexadecimal codes
    • BCD code
    • Excess-3 code
    • Gray code
    • Examples of code conversions
  • 1.7 Alphanumeric codes: ASCII code and EBCDIC code
  • 1.8 1’s complement and 2’s complement
  • 1.9 Signed number representation

2Logic Gates3 hours

Logic gates, universal gates and De Morgan's laws.

  • 2.1 Basic gates and their equivalents
  • 2.2 Universal gates and their equivalents
  • 2.3 Exclusive gates and their equivalents
  • 2.4 Positive and negative logic
  • 2.5 De’Morgan’s laws
  • 2.6 Applications of logic gates

3Boolean Algebra and K-Maps4 hours

Boolean algebra and Karnaugh maps up to four variables, including don't-care conditions. Practise many K-maps; grouping quickly and correctly is a skill.

  • 3.1 Boolean algebra and its laws
  • 3.2 Simplifications of Boolean expressions
  • 3.3 Minterms and maxterms
  • 3.4 Sum-of-product and product-of-sum methods
  • 3.5 Truth tables and Karnaugh map
  • 3.6 Four variables K-maps.
  • 3.7 Cell, pairs, quads and octets
  • 3.8 Rolling, envelop effects and redundant groups
  • 3.9 Don’t care conditions

4Combinational Logic Circuits8 hours

Combinational circuits, 8 hours and 10 of 60 marks: adders, subtractors, multiplexers, decoders, encoders and comparators. Follow the design procedure each time: truth table, simplify, draw.

  • 4.1 Design procedures
  • 4.2 Half-adder and full-adder
  • 4.3 Half-subtractor and full-subtractor
  • 4.4 Ripple carry adders and fast adders
  • 4.5 Multiplexers design
  • 4.6 Demultiplexers design
  • 4.7 Basic encoders
  • 4.8 Priority encoders
  • 4.9 Encoder designs
  • 4.10 Decoder designs
  • 4.11 BCD-to-decimal decoder
  • 4.12 Seven-segment decoder
  • 4.13 Magnitude comparators

5Sequential Logic Circuits5 hours

Latches and SR, D, T and JK flip-flops, with excitation tables and conversions between flip-flop types.

  • 5.1 Latches and flip-flops: SR, D, T and JK
  • 5.2 Excitation tables, characteristic equations
  • 5.3 Master-slave flip-flops
  • 5.4 Flip-flop timing diagrams
  • 5.5 Flip-flops as the state machines
  • 5.6 Flip-flop conversions
  • 5.7 Flip-flop applications

6Registers and Counters7 hours

Registers and counters, 10 marks. Draw timing diagrams by hand for both asynchronous and synchronous counters until they are routine.

  • 6.1 Register fundamentals, register types
  • 6.2 SISO, SIPO, PISO and PIPO registers
  • 6.3 Data transfer timing diagrams
  • 6.4 Asynchronous counters
  • 6.5 Up, down and mod-n asynchronous counters
  • 6.6 Synchronous counters
  • 6.7 Up, down and mod-n synchronous counters
  • 6.8 Register and counter applications

7Sequential Machine Designs8 hours

Sequential machine design, also 10 marks and 8 hours. The sequence detector is the classic problem; work it from state diagram to circuit several times.

  • 7.1 Machine design procedures
  • 7.2 Primitive state diagrams
  • 7.3 Transition/flow tables
  • 7.4 Redundant states
  • 7.5 Pure binary assignment tables
  • 7.6 Excitation maps
  • 7.7 Realization of the models
  • 7.8 Circuit diagram of synchronous machine
  • 7.9 One-bit and two-bit input sequence detectors

8Digital Integrated Circuits5 hours

TTL and CMOS logic families and their parameters, the physical side of the course.

  • 8.1 BJT and MOSFET switching circuits
  • 8.2 TTL parameters
  • 8.3 TTL circuits: NAND, NOT, NOR
  • 8.4 CMOS parameters
  • 8.5 CMOS logic circuits: NAND, NOR, NOT
  • 8.6 Three-state TTL devices
  • 8.7 Digital devices applications
    • Multiplexing displays
    • Frequency counters
    • Time measurements

Laboratory

The ENEX 152 practical

The laboratory is three hours a week through ten experiments: basic and universal gates, De Morgan's law, encoders and decoders, multiplexers, binary addition and subtraction, flip-flops, shift registers, and ripple and synchronous counters. Build each circuit on a breadboard yourself and predict the output before switching on.

  1. Basic gates, universal gates and exclusive gates
  2. De' Morgan’s law and its familiarization with NAND and NOR Gates
  3. Encoders and decoders
  4. Multiplexers and demultiplexers
  5. Binary addition and subtraction
  6. Latches, RS, and T flip-flops.
  7. D and JK flip-flop and master-slave flip-flop
  8. Shift registers
  9. Circuit realizations on ripple counters
  10. Circuit realizations on synchronous counters

Reference books

Books IOE lists for ENEX 152

  1. Floyd, T. L. (2015). Digital fundamentals. Pearson Education.
  2. Mano, M. M. (1995). Digital design (Latest Edition). Prentice Hall.
  3. Leach, D.P., Malvino, A.P., Saha, G. (2012). Digital principles and applications. Tata McGraw-Hill Education.
  4. Fletcher, W.I. (1980). An engineering approach to digital design (Latest Edition). Prentice-Hall.
  5. Gothmann, W.H. (1982). Digital electronics: An introduction to theory and practice (Latest Edition). Prentice-Hall.

Quick answers

Digital Logic questions

Which chapters of Digital Logic carry the most marks?

Combinational Logic Circuits, Registers and Counters, and Sequential Machine Designs, 10 marks each out of 60 in IOE's scheme.

Is Digital Logic taught in both BCT and BEI?

Yes. Computer and BEI students both take ENEX 152 in Semester 2 with the same outline.

What comes after Digital Logic?

Microprocessors (ENEX 201) in Semester 3, which uses the registers, counters and state machines from this course.

How many credits and marks is ENEX 152 Digital Logic?

3 credits and 150 marks: 40 internal and 60 in a 3-hour IOE final for theory, plus 50 marks of practical assessed internally. It is taught 3 lecture, 1 tutorial and 3 practical hours a week.

Source

Checked against IOE

The outline, references and marks are IOE's own, from the ENEX 152 syllabus PDF and IOE's curriculum structure. The study advice is ICE's. If IOE revises the course, its syllabus is what counts. IOE's BCT curriculum page.

Last reviewed by Imperial College of Engineering. Outline and marks checked against IOE's syllabus PDF; study advice written by ICE.