Intel details a 256-core Xeon and an inference GPU at Hot Chips

What happened

Hot Chips is a yearly conference where chip companies explain how their processors are built inside. In 2026 Intel used it to present three products that it says cover everything from large server racks to small edge devices. Intel's chief technology officer, Pushkar Ranade, said all three rely on Intel Foundry technology: the Intel 18A family of manufacturing processes, a 3D stacking method called Foveros Direct, and an open standard for linking chiplets called UCIe. A day later the market research firm TrendForce collected further details from several technical news sites.

Diamond Rapids is the next Xeon server processor. Intel says it has up to 256 cores, 1.28 GB of last-level cache and 16 memory channels running at 12,800 million transfers per second. It also offers 128 lanes of PCIe 6.0 (Peripheral Component Interconnect Express, the standard slot link for cards and drives) and supports CXL 3.0 (Compute Express Link). TechPowerUp, as summarised by TrendForce, reports 16 core chiplets made on the 18A-P process, each with 16 cores. These sit on four base tiles made on Intel 3, and each tile holds 320 MB of cache shared by 64 cores. TrendForce, citing ServeTheHome, says launch is planned for 2027.

Crescent Island is a data-centre graphics card built only for inference, which means running AI models that are already trained. Intel says it has 32 Xe3P cores and 256 matrix engines, draws up to 350 watts and is cooled by air. TrendForce reports that Intel's own card carries 160 GB of LPDDR5X (low-power double data rate) memory, and that designs from partner manufacturers can hold up to 480 GB. Wildcat Lake, sold as Intel Core Series 3, is made on Intel 18A. It has two performance cores, four efficiency cores and a neural processing unit rated at up to 17 TOPS (trillion operations per second).

The engineering behind it

For many years a processor was one large piece of silicon, called a monolithic die. Large dies are expensive, because one small defect anywhere can ruin the whole chip, and the share of good chips falls as dies get bigger. A chiplet design splits the processor into several smaller dies and joins them inside one package. Each small die is easier to make without defects, and different parts can use different manufacturing processes. Diamond Rapids follows this pattern. Its cores use the newer 18A-P process, while the cache tiles and the hub tiles that handle input and output use the older Intel 3 process.

Diamond Rapids also stacks dies on top of each other. According to ServeTheHome, as reported by TrendForce, the core chiplets are bonded directly onto the base tiles below them using Foveros Direct 3D hybrid bonding. In general, stacking places the cache very close to the cores, so data travels a shorter distance. A shorter path usually means less delay and less energy for each transfer. The cost is heat and complexity, because a stacked chip is harder to cool and harder to test than a flat one.

Crescent Island shows a different engineering choice. Many high-end AI accelerators use high-bandwidth memory, which is very fast but expensive and limited in supply. Crescent Island uses LPDDR5X instead, a lower-power memory type first designed for phones and laptops. In general it gives less bandwidth but more capacity for the money. TrendForce says the card supports FP4, a 4-bit floating-point number format, alongside 8-bit FP8. Smaller number formats store each model weight in fewer bits, so a large model fits in less memory and runs faster, with some loss of precision.

UCIe, short for Universal Chiplet Interconnect Express, is an industry standard for how chiplets talk to each other inside one package. A shared standard means chiplets from different designs can, in principle, be combined. Intel says Wildcat Lake is the first Intel processor to use it. TrendForce, citing Wccftech, adds that Wildcat Lake drops the 3D Foveros packaging of the earlier Panther Lake chip and uses a cheaper organic multi-chip package. That change removes a base die and, the report says, lowers assembly cost and the number of chips lost to defects.

What it means in Nepal

None of the sources mention Nepal, and these chips are designed and made abroad. What they show is the direction of the hardware that engineers everywhere will buy, program and maintain. Servers in data centres, laptops in classrooms and computers on factory floors are moving towards chiplet designs, with separate units for general computing, graphics and AI work. An engineer who understands why a chip is built this way can make better decisions about which hardware fits a task and a budget.

The Crescent Island design also teaches a lesson that applies in any country. The best technical choice is not always the fastest part. Intel chose air cooling, a 350-watt limit and cheaper memory so that, by its own account, the card fits into data centres that already exist. Weighing speed against power, cooling, cost and supply is a normal part of engineering work. The same thinking applies to a student choosing a microcontroller for a project, or to an IT team choosing servers for an office.

For students who want to work close to hardware, the ideas behind these chips can be learned during a degree. They include digital logic design, cache and memory hierarchy, number formats, and the way an operating system shares work across many cores. Software developers benefit too. A program that ignores cache and memory layout can run much slower than it should on a machine with hundreds of cores, so this knowledge is useful well beyond chip design.